To fabricate a package where a semiconductor chip is mounted onto a substrate, for example, the connection pad of the semiconductor chip and the connection pad of the substrate are bonded and electrically connected via bumps. Also to mount a package onto a circuit board, for example, a land of the package and a land of the circuit board are bonded and electrically connected via bumps. In both cases, a possible problem is an impedance mismatch due to reflection loss or the like in the connection portions, and impedance drops because of the difference of sizes between the wiring routed to the pad and the land, and the pad, land or bump. This problem is particularly conspicuous in a high-speed signal transmission area, such as the GHz band.
Patent Document 1 discloses that a bonding portion wiring formed on a substrate and a chip bonding portion of a semiconductor chip face each other and are bonded to each other, whereby the substrate and the semiconductor chip are electrically connected. The size of the bonding portion wiring and the size of the bonding portion of the chip, according to Patent Document 1, are different from each other.
Patent Document 2 discloses that a wiring on the top surface of the circuit board and a wiring on the top surface of a surface mount device are connected via the inclined plane of the surface mount device, whereby the surface mount device is mounted on the circuit board. Both the wiring of the circuit board and the wiring of the surface mount device, according to Patent Document 2, face up, and the end portions of each wiring are butt-connected to each other.    Patent Document 1: Japanese Patent Application No. 2000-183231A (paragraph 0053, FIG. 1)    Patent Document 2: Japanese Patent Application No. 2010-21505A (paragraphs 0021 to 0022, FIG. 4)